Georgia Institute of Technology Materials Science and Engineering

Committee Members: 

Prof. Rao Tummala, Advisor, MSE/ECE

Prof. Madhavan Swaminathan, MSE/ECE

Prof. C. P. Wong, MSE

Mohanalingam Kathaperumal, Ph.D., ECE

Leonel Arana, Ph.D., Intel Corporation

Abstract: 

Transistors are the fundamental building blocks of all electronic devices. Miniaturization of transistors from node to node, leading to higher transistor performance, has been the key driver of technological progress over the last six decades. Moore’s law states that the number of transistors on an integrated circuit (IC) chip doubles approximately every two years. However, transistor performance improvement from node to node has slowed down considerably in recent years. The demand for higher computational power, however, is more than ever, especially for applications such as artificial intelligence (AI). To keep up with this ever-increasing demand for higher computational power, new ways are being explored, including the concept of ‘Moore’s Law for Packaging or Interconnections’ by Prof. Tummala. In this concept, the focus is on achieving higher total performance between transistors and interconnects by combining the best of Moore’s law for ICs with Moore’s law for interconnections.  Integration of multiple smaller chips with higher transistor density, together with higher interconnect density, are gaining importance in high-performance computing (HPC) applications. Higher bandwidth requiring higher density of interconnections between two or more chips is, therefore, critical for achieving superior computing performance.

One way of achieving higher bandwidth is by increasing the input and output (IO) density by scaling redistribution layers (RDL). The pace of package RDL scaling has not been as aggressive as transistor-scaling over the years. But this is changing dramatically. The goal of this thesis is to try to address this issue by designing and demonstrating highly reliable and high-bandwidth package RDL with minimum conductor linewidth and spacing (L/S) of 1 µm. This will lead to a five-fold increase in the package RDL IO-density over the current state-of-the-art.

The main focus of the proposed research is to demonstrate the mechanical and electrical reliability of RDL which is of paramount importance as the conductor linewidth and spacing are scaled to 1 mm.  The mechanical reliability issues in RDL arise from the mismatch in the physical properties of the materials (substrate, dielectric and conductor) involved. This results in the development of stresses at various interfaces during fabrication and during the operation of devices. Accumulation of stresses leads to failure of RDL wiring due to delamination, excessive warpage, fatigue, and dielectric cracking thus compromising the performance of the system. The electrical reliability issues arise from the migration of ionic impurities in the build-up dielectrics, as well as electromigration leading to an increase in conductor line resistance or shorting of the adjacent lines. The proposed research is aimed at addressing these challenges as the RDL IO-density is increased to achieve higher computing performances.